The present invention relates to controllers for dynamic memories, and particularly to integrated circuits which control DRAM memory.
The disclosed preferred embodiments provide a DRAM controller which
"serializes" and PA1 "nonvolatizes" a bank of DRAMs, while PA1 providing multi-generation flexibility, PA1 providing refresh control which is totally transparent to the system, and PA1 providing various overhead management functions.
To appreciate the interrelation and desirability of these features, and the specific innovative implementations used to achieve them, various general aspects of the DRAM art will first be reviewed.
DRAMs from the System Designer's Point of View
DRAMs are the lowest-cost type of semiconductor memory. DRAMs are therefore used in a very wide variety of computer systems, and in other electronic systems as well.
Refreshing Requirements
DRAM memories require refreshing. In a DRAM, information is represented by the presence or absence of electric charge in storage capacitors in the DRAM cell. (For example, a "1" might be written into a DRAM cell by storing a packet of charge in the cell, and a "0" by not storing a packet of charge.) However, these packets of charge are very small, and they rapidly leak away. Depending on various factors, the data stored in a DRAM cell may become unreadable within less than 1/10th of a second after it has been written.
Therefore, to maintain stable storage of data, it is necessary to periodically read out each of the cells in the chip, amplify the data signal from the cell, and write the amplified data signal back into the cell. This function is well known to those skilled in the art of computer memory system design. Many chips are available to perform "memory management" functions, such as determining when another refresh cycle must be initiated for the DRAM chips in a memory bank.
Unless a DRAM receives refresh signals and power, the stored data will be lost. Therefore, the data in a conventional memory bank composed of DRAMs will disappear whenever a significant power interruption occurs. It would be highly desirable to avoid this vulnerability to power interruption, but no commercially feasible way to accomplish this has yet been presented.
Control of DRAM Refresh Timing
The need for refreshing, which is dictated by the inherent structure of DRAM memory cells, implies some inherent conflict: DRAMs must be refreshed periodically, but the refreshing operations should preferably interfere with memory access as little as possible.
The computer system which attempts to access the data in DRAMs will typically not known what the refresh status of the DRAM chips is. Therefore, if the system attempts to access the chip during a refresh cycle, the system may be told to wait (that is, a "wait state" is generated). This is inefficient.
The timing of refresh cycles is somewhat flexible, and therefore the designers of DRAM control circuits have tried, in various ways, to perform the refresh cycles during periods when memory access is not occurring. Still, there is some inherent conflict. One approach to this is known in U.S. Pat. No. 4,028,675 to Frankenberg (which is hereby incorporated by reference), which appears to suggest a sort of arbitration scheme, in which wait state may still sometimes be generated.
Variable DRAM Refresh Timing
Another advantageous teaching provided by the DRAM controller of the present invention is selectable refresh periods. (For example, in the presently preferred embodiment, the controller chip can be programmed to refresh the DRAM chip(s) at intervals of as little as 4 ms, or as long as =ms.) This capability can be used by systems integrators in at least two ways: first, the controller can be programmed to match the characteristics of whatever DRAM memories are actually used in the finished system. Thus, in power-critical applications, DMAM chips with tighter specifications on refresh timing can be used, while other applications, cheaper DRAM chips can be used, and the controller can be programmed to optimally match the characteristics of whichever type are used.
In applications where power conservation is critical, the refresh rate provided by the DRAM controller of the presently preferred embodiment can be adjusted dynamically on the fly, to optimize refresh cycle timing for the actual data retention times of the memories being used at a particular moment. For example, this capability can be used to provide temperature-dependent variable refresh intervals in a low power system using DRAMs.
The controller chip of the present preferred embodiment also includes control options which permit it to work with DRAM chips which have a wide variety of speeds. Thus, this controller can be used in combination with extremely cheap memory chips, to provide low-cost bulk solid state memory, without being limited to low-speed memory operation.
Interfacing to Multiple Generation of DRAMs
The rapid evolution of DRAMs is advantageous to users, but can be somewhat inconvenient in designing a system architecture. DRAM densities advance by one full generation about every 3 years. Thus, for example, the 16K DRAMs which were commercially dominant in the late 1970s were successively superseded, over the next decade, by 64K, 256K, and 1M DRAMs. Since the lifetime of a computer system architecture can be significantly longer than that of a DRAM generation, the system architecture should be able to interface to new generations, or the architecture will become obsolete for that reason alone. Moreover, at any one time, 2 or 3 different densities will be prevalent in the marketplace, since users will make their own choices in view of cost per bit, system costs, speed, reliability, physical density, power dissipation, etc.
Thus, it is highly desirable for the computer system architecture to be able to be used with more than one density of DRAM. However, there are some difficulties in achieving this. Some discussion of the problems of multigeneration DRAM adaptability may be found in U.S. Pat. No. 4,676,808 ("Multiplexed-address interface for the addressing memories of various sizes"--Grinn et al.).
Note that conventional addressing architectures pose some degree of incompatibility among different generations of memories. For example, in a normal 1M DRAM, the 20 address bits A0 through A19 would typically be allocated with bits A0 through A9 (for example) used for the column address, and bits A10 through A19 used for the row address. Thus, A9 is the most significant bit of the column address, and A19 is the most significant bit of the row address. If the address field is expanded by two bits (to scale to a four megabit RAM), using the same allocation of the logical address field, A10 would now be the most significant column address bit, rather than the least significant row address bit, and A21 would be the most significant row address bit. Thus, straightforward expansion would interfere with the sequencing nodes normally used to implement the refresh timing or serial access operations. Therefore, to provide multigeneration compatibility, the DRAM controller of the present invention remaps the logical address field, so that the more significant row and column address bits (which are needed for the higher-density memories of later generations) are added onto one end of the address word format. Thus, the presence or absence of these bits does not disturb the initial allocation of the minimum set of the address bits into row and column address bits.
The presently preferred embodiment provides a DRAM controller which can be directly connected, without any automatic or selected reconfiguration to DRAMs of various sizes. This is accomplished by remapping the externally-received address bits, so that the most significant two bits of address are remapped onto the most significant bit of a row address and the most significant bit of a column address. Similarly, the next two most significant bits of address are remapped onto the second most significant row bit and the second most significant column bit. This remapping does not affect the system interface, since the address bit remapping only affects the physical location of the memory cell corresponding to a given logical address, but does not change the characteristics of the logical address space as a whole. Thus, the external system can ignore the actual physical organization of the addressed cells.
The address bit remapping permits memories of any one of four generations to be directly connected to the controller chip of the presently preferred embodiment. For example, the controller chip of the preferred embodiment can be directly connected to memory chips of 256K, 1 megabit (1M), 4M, or 16M. By extending the disclosed innovative ideas, other densities (higher or lower) can be accommodated, or more or fewer than four densities can be accommodated.
Some form of address remapping appears to be disclosed in U.S. Pat. No. 4,675,808 to Grinn et al, which is hereby incorporated by reference. However, the scheme disclosed in the Grinn et al. patent apparently requires one more address line than would be required for the largest addressable memory size. The teaching of the Grinn et al. patent is thus believed to be significantly different from that disclosed herein.
Making DRAMs Nonvolatile
A significant development in system architectures during the 1980s has been the use of nonvolatized semiconductor memory. For example, many systems currently use SRAMs which are combined with a small battery, so that the data in the memories is not lost if the system power is interrupted.
SRAMs (static random access memories), like DRAMs, are volatile. That is, SRAMs too will lose their data as soon as power is interrupted. However, a relatively recent development has permitted systems using SRAMs to achieve nonvolatility. The SmartSocket (TM), marketed by Dallas Semiconductor Corporation, is a socket which includes a small lithium battery and a controller circuit, so that a CMOS SRAM can be maintained in standby status when the system power supply fails. This product has proven to be extremely useful to system designers.
DRAMs, unlike SRAMs, do not have a very low power standby mode, and do require refresh operation. These factors make it more difficult to implement battery backup for DRAM memory. Another difficulty is that DRAMs tend to be more sensitive to power supply voltage fluctuations than SRAMs are.
The present invention is most preferably used for memory subsystems where standard commercial DRAMs can be used, but wherein the data in the DRAMs is nonvolatized, i.e. is safeguarded against power failure. A controller for making DRAMs appear nonvolatile is disclosed in commonly owned application Ser. No. 248,865, filed 9/23/88 which is hereby incorporated by reference.
Serial Access to DRAMs
From the system designer's point of view, serial access has many distinctive features which will continue to make it advantageous for some applications. Serial access can provide a robust, well-understood data interface, with great flexibility in system configuration, at the cost (normally) of some limitation in maximum data rate.
The disclosed preferred embodiment provides a DRAM controller which "serializes" and "nonvolatizes" a bank of DRAMs, while providing multigeneration flexibility and refresh control which is totally transparent to the system.
A quite differently motivated approach to the questions of serial access to DRAMs can be found in the video DRAM art generally, and also in publications such as U.S. Pat. No. 4,847,809 ("Image memory having standard dynamic RAM chips"), which is hereby incorporated by reference. It should be noted, however, that the high-speed serial access used in video DRAMs offers significantly different issues from the serial access provided by the present invention. The motivation for serial access in video memories is usually the need to read out an image frame in real-time, at full video data rates (typically 10-50 MHz).
Refresh Timing Control is a Serial-Access DRAM
In the preferred chip embodiment, many aspects of the refresh control and battery backup functions are generally similar to those described in U.S. patent application Ser. No. 248,865, field 9/23/88, which is hereby incorporated by reference. However, the presently preferred embodiment contains additional features, related to the control of refresh timing in a DRAM module which is serially accessed, which are believed to be novel.
In the presently preferred embodiment, the serial overhead protocol provides for burst read and burst write modes, in addition to the normal read and write modes. When the chip is operating in a burst mode, every clock will produce a new memory access (read or write). To escape the burst access modes, the reset line (RST) is pulled high.
An on-chip tapped delay line is used to provide refresh timing. Since refresh timing is typically not very critical, the precision of this delay line is not critical. Trimming of the delay elements can be done on a wafer-by-wafer basis or not at all.
The refresh requirements of a serial access DRAM controller differ somewhat from those of a conventional DRAM system architecture. It is most preferable that the refresh operations be interleaved with user memory access, so that user memory access is not impeded by delays for refresh operations unless absolutely necessary.
One scheme which mist be considered is to do the refreshes on the high clock cycle, and then data accesses on the low state of the clock. However, this implies an inconvenient limit on the user's frequency of access while the memory is active: the user would have to perform enough accesses (e.g. more than 512) within the refresh interval (e.g. every 8 milliseconds) to maintain the memory cells in a refresh condition while the chip is active.
The presently preferred embodiment avoids such constraints, at the cost of adding some pipelining functionality to architecture. Each falling edge of the clock line CLK is followed by a refresh cycle, and every rising edge of CLK is followed by an active cycle. Since the clock cycles are allowed to have variable duration, a rising edge may not be followed immediately by a falling edge, and a falling edge may not be followed immediately by a rising edge. To prevent sensitivity to such variable clock circumstances, any falling edge which is not immediately followed by a rising edge will permit multiple refresh cycles to occur. Similarly, any rising edge after which the clock line remains high for more than one clock period will initially be followed by an active cycle, which is then followed by one or more refresh cycles, until the clock line goes low and then goes high again.
Thus, this simple organization allows the active cycles to always have priority, but all remaining time is filled with refresh cycles. Thus, the memory can stay maximally refreshed, without any interference with data access operations under normal conditions. Note that the rising edge of the clock loads a pipeline internal register with the data needed for the ensuing active cycle. In the presently preferred embodiment, the DRAM controller chip is operated at a maximum clock rate of 1MHz. Of course, a wide variety of clock rates can be used instead, including slower or (more preferably) faster clock rates.
In the presently preferred embodiment, the refresh operations are in fact performed as burst refresh operations, rather than continuous refresh operations. This helps to save power and minimize heat dissipation: a 1M DRAM in continuous refresh will typically draw around 70 milliamps of current. If the reset line RST* is brought high during a refresh cycle while the chip is in standby mode, then part of the refresh burst will be stretched.
When power fails, it would be simplest to initiate refresh as soon as possible. However, the risk is that the chip may have been in the middle of a data access. The presently preferred embodiment avoids this risk by allowing any refresh cycle in progress to be completed before an active cycle is allowed to begin.
In this embodiment, each cycle is identified as a refresh cycle, an active cycle, or an idle cycle. A state machine circuit is used to implement this: at the start of a new cycle, the state machine determines the cycle type and drives appropriate lines.
System Embodiments
One innovative system embodiment, using the disclosed innovative memory controller, is a voice recording storage module. In such a module, a serialized DRAM memory (including a controller as described below and one or more DRAM chips) is combined on a SIP module with a battery and voice compression hardware (such as the DS2167 ADPCM chip from Dallas Semiconductor), together with another controller which controls the data interface functions.
A further advantageous system application of the disclosed memory controller is a new type of disk emulation. The "RAM disks" presently available perform disk emulation in software (using memory which has a largely conventional hardware architecture). By contrast, a block of serialized DRAM according to the present invention can be used to provide a hard-disk-emulating solid-state memory which is, insofar as seen by the interface to the system, a perfect match for the characteristics of a hard disk, except that such a emulator can be made much faster than a hard disk and much more rugged.